COMMITTEE CHAIR: Dr. Suxia Cui

TITLE: ADVANCING THE HARDWARE REALIZATION OF SWINIR FUNCTIONS

ABSTRACT: Image enhancement is a key area in image processing that aims to improve visual quality for interpretation, analysis, and decision-making. SWINIR (Shifted Window Image Restoration) is a state-of-the-art deep learning model for image superresolution; however, mapping its computation pipeline to hardware is challenging due to its hierarchical attention structure and the computational complexity of core operations such as Softmax, dot-product accumulation, and exponential evaluation. This work investigates hardware-efficient approaches to implement these core functions to enable practical deployment of SWINIR on resource-constrained platforms. A detailed review of existing accelerator designs is presented, focusing on optimizations for the AI functions processing. For example, various techniques for implementing the exponential function are examined; including lookup tables, CORDIC, and logarithmic base-2 approximation methods. This work identifies the use of BRAM LUTs to store exponential values or to store the 2(fractions) part when using Base-2 of the natural log approach; as a limitation to how much tiled processing can be performed, and adopts a fourth-order Maclaurin series approximation for the exponential function as a balanced solution between computational cost, accuracy, speed, and hardware area. A correction strategy is introduced to mitigate approximation distortion within the attention computation range, enabling efficient fixed-point hardware realization without large lookup tables or slow iterative units. By avoiding floating-point division through range normalization strategies, the proposed approach reduces both resource usage and latency; reducing DDR traffic and increasing throughput in the softmax vectors per second compared to using BRAM-LUTs. Only limited by available DSPs now. This work also introduces branching into the systolic additions module for additional speed from the additions module. This work provides the architectural foundation for a hardware implementation of SWINIR targeting low-cost FPGA devices suitable for edge applications. The proposed methods emphasize; more BRAM space made available for tiled processing, acceptable image quality with PSNR gains where possible, and scalability for integration into a full SWINIR hardware pipeline. This work will also focus on implementing and validating the complete system on a small FPGA, demonstrating cost efficiency and feasibility on small FPGA improvements compared to existing high-resource FPGA and cloud-based implementations.

Keywords: Image Enhancement, FPGA, SWINIR, Energy Efficiency

Room Location: Electrical Engineering Building Room 315D