COMMITTEE CHAIR: Dr. Cajetan Akujuobi

TITLE: DESIGN AND HARDWARE VALIDATION OF A 5G NR OFDM TRANSMITTER ON THE INTEL DE10-NANO FPGA

ABSTRACT: Fifth generation (5G) wireless networks have made Orthogonal Frequency Division Multiplexing (OFDM) the backbone of modern physical-layer communication, enabling high spectral efficiency, resilience to multipath fading, and support for everything from smartphones to industrial sensors. Field Programmable Gate Arrays (FPGAs) are a natural choice for prototyping these systems: they are reconfigurable, support massive parallelism, and behave predictably in real time. Even so, moving from a clean floating-point Simulink simulation to a working, fixed-point FPGA implementation is far harder than it looks, and that gap is poorly documented in the existing literature. This thesis walks through the full journey. Starting from a behavioral MATLAB/Simulink model of a 5G NR OFDM transmitter, the work covers fixed-point optimization, VHDL code generation using MATLAB HDL Coder, synthesis and compilation in Intel Quartus Prime, deployment onto the Intel DE10-Nano development board, and real-time hardware verification using Intel SignalTap Logic Analyzer. The transmitter implements 16-point Quadrature Amplitude Modulation (16-QAM) symbol mapping via a 2-D Lookup Table (LUT), a FIFO-based streaming buffer, and a 64-point radix-2² Streaming Delay-Feedback IFFT core with approximately 118 cycles of pipeline latency, all wrapped in an Advanced eXtensible Interface 4-Stream (AXI4-Stream)-compatible handshake interface. Using 4-bit symbol inputs and 8-bit data paths throughout, the design achieved zero DSP block utilization and consumed approximately 3% of all available Cyclone V resources: 1,095 of 41,910 Adaptive Logic Modules (ALMs), 2,892 registers, and 78,144 block memory bits. Timing analysis confirmed a positive setup slack of 9.429 ns at 50 MHz across worst-case temperature corners. SignalTap captured live waveforms from 12 internal pipeline nodes, including FIFO occupancy, QAM-mapped symbol data, IFFT input and output, and twiddle factor phase sequencing, and all 12 verification criteria passed. BER simulation in MATLAB confirmed error-free operation at SNR values above 18 dB for 16-QAM over an Additive White Gaussian Noise (AWGN) channel. This thesis makes five original contributions, each grounded in implementation methodology and hardware evidence rather than algorithmic novelty: a hardware-verified VHDL implementation of a 5G NR-inspired OFDM transmitter baseband subsystem on the DE10-Nano; a fixed-point optimization strategy that eliminates DSP block usage entirely while preserving correct BER performance; to the best of the author’s knowledge, one of the few documented applications of SignalTap to verify an HDL Coder-generated 5G NR Physical Layer (PHY) design; a practical debugging methodology for the HDL Coder-to-Quartus Prime workflow; and concrete evidence that 5G NR physical layer prototyping is achievable on low-cost, accessible hardware using freely available tools.

Keywords: 5G NR, OFDM, FPGA, DE10-Nano, Cyclone V, HDL Coder, Simulink, Fixed-Point, SignalTap, 16-QAM, IFFT, Hardware Verification

Room Location: Electrical Engineering Conference Room 315D