Akanimo Etokebe Dissertation Proposal Defense, Thursday, April 23, 2026 @ 10:00 am Central Time

COMMITTEE CHAIR: Dr. Suxia Cui

TITLE: CNN-BASED IMAGE ENHANCEMENT USING SPARSITY-AWARE OPTIMIZATION

ABSTRACT: The deployment of convolutional neural network (CNN)-based image enhancement in edge computing environments is constrained by limited hardware resources and strict power budgets. Although CNN architectures provide superior visual restoration performance compared to traditional filtering techniques, convolution operations exhibit high multiply–accumulate (MAC) density and memory access intensity, resulting in elevated dynamic power consumption on resource-constrained FPGA platforms. In CMOS-based programmable logic, dynamic power is dominated by switching activity and can be modeled as Pdyn = aCV2f, where a represents the signal transition probability. Dense convolution architectures maintain continuous activation of DSP blocks and routing fabric, leading to high switching activity and reduced energy efficiency. This report presents a sparsity-aware systolic array architecture for CNN-based image enhancement implemented on the Zybo Z7-20 FPGA platform (Zynq-7020 SoC). A baseline dense systolic implementation is first developed and characterized in terms of resource utilization, throughput, and power consumption. The proposed optimization introduces zero-skipping mechanisms, selective MAC gating, and bypass datapaths to exploit weight and activation sparsity. By reducing unnecessary operand propagation and disabling idle DSP48E1 slices, the architecture lowers effective switching activity within the convolution engine and interconnect network. The system is implemented in Verilog-2005 and synthesized using Vivado 2023.1. Experimental results demonstrate a measured 39% reduction in total power consumption compared to the dense baseline, while maintaining functional correctness and enhancement quality. Image quality evaluation using noisy butterfly datasets shows an improvement in Peak Signal-to-Noise Ratio (PSNR) from 16.2 dB to 19.6 dB. Resource utilization remains within the 220 DSP slice and limited Block RAM constraints of the Zybo Z7-20 device. These results demonstrate that CNN-based image enhancement on resource-constrained FPGAs can achieve high-quality visual restoration while significantly reducing dynamic power through sparsity-aware systolic processing. The proposed approach advances energy-efficient edge AI acceleration by integrating sparsity exploitation, hardware-level switching activity reduction, and structured systolic dataflow optimization within an embedded vision framework.

Keywords: Convolution Neural Network, Hardware Resources, Systolic Array, Power Consumption, Sparsity Exploitation

Room Location: Electrical Engineering Conference Room 315D